This invention relates to a precharging circuit and, more specifically, to a data bus precharging circuit for use in circuit devices having data buses.
Monolithic integrated circuit devices such as read-only memories (ROMs), random access memories (RAMs), and central processing units (CPUs) include data buses for selectively sending and receiving data signals. In general, every bit line of the common data bus in such devices in initialized to a logic "1" (a power source potential V.sub.DD) before data signals in one internal memory circuit are sent to another internal memory circuit. However, due to the parastic capacitance associated with every bit line of the data bus, it will take a long period of time, for example, 150 to 300 nanoseconds, to establish data signals on the data bus after every bit of the data bus has been initialized with a logic "1" or a power source potential V.sub.DD. To avoid this problem, a data bus precharging circuit has been commonly employed for the data bus to establish the initial condition of the data bus at a high speed.
The data bus precharging circuit is a charging circuit for decreasing the time required for the initial condition of the data bus by forcibly establishing a logic "1" on every bit line of the data bus, before the data signal will be set on the data bus.
In general, one state cycle for sending data in one memory circuit, such as a register, to another memory circuit, such as a register, includes three steps as follows:
In the first step, when the precharging circuit is inputted with a precharging control signal, the data bus is precharged to a power source potential (a logic "1") by the output signal therefrom.
In the second step, when a read signal is inputted into a selected internal register, data signals from the register are outputted to the data bus.
In the third step, when a write signal is inputted into another internal register, data signals on the bus are stored therein.
However, a prior art precharging circuit requires three independent signal sources for generating a precharging control signal, a read signal, and a write signal, respectively. Also, the prior art precharging circuit has a disadvantage in that one state cycle needs a clock signal of three to five cycles, thereby taking a long operational time for processing data in one state.
Furthermore, the prior art circuit has another disadvantage in that it places the bus in a set condition, or in a logic "1" state, during a fixed cycle so that the time to set the data into the data bus become longer. For example, in the prior art circuit used in a monolithic integrate CPU (Central Processing Unit) was difficult to realize a state cycle time of less than 100 nanoseconds.